A Digital Experience

Dermot O’Driscoll leads Arm’s Product Solutions organization for the Infrastructure Line of Business. His responsibilities include definition, delivery and successful deployment of Arm-based products across the range of Infrastructure segments. With a detailed knowledge of datacenter and networking applications he leads a team responsible for Arm’s IP and Software products in those markets. Mr. O’Driscoll works with Arm’s partners to enable development of class leading SOCs, and engages OEMs and Cloud Service Providers (CSPs) to ensure successful deployment of efficient Arm-based solutions.

Yufeng Luo is Vice President R&D leading the Digital Design Implementation (DDI) business unit at Cadence, and is responsible for the product development of Genus, Innovus, and Joules. He joined Cadence in 2012, and was the main architect of the innovative GigaPlace technology in Innovus. Before Cadence, Yufeng spent time at Synopsys from 1997 to 2003, and Sierra Design Automation/Mentor Graphics from 2003 to 2012, leading various EDA projects. Yufeng has a MSEE from the University of Texas at Austin, and BSEE from Shanghai Jiaotong University.

Ravi is the Product Engineering Engagement Architect at Cadence focused on ARM CPU implementation. Ravi has more than 20 years design implementation experience, specific to CPU designs. Prior to joining Cadence, Ravi was SOC full chip timing lead at Intel, where he was responsible for Intel’s Mobile SOC timing closure and worked on various CPU implementation projects with Intel. Ravi was with Intel for 14 years, where he held a variety of Design implementation and Development leadership roles. Ravi earned a Bachelor of Engineering from Osmania University, Hyderabad India and an M.S from OGI Oregon.

Krishna joined Arm in 2005, and has been involved in physical design/implementation of Cortex A/X class CPUs, and Neoverse V/N class CPUs coming out of Austin CPU design center, ever since. He is working with Cadence tools for almost and continues engagement on new methodologies, the latest being hierarchical flows. Arm successfully deployed this flow for current generation of CPUs, and switched to this flow as baseline for future CPU implementations coming out of Austin.

Brian Wallace joined Cadence in 1997 and is currently an Application Engineer Architect in the Digital Implementation & Signoff Group. Brian has over 20 years of experience in EDA developing flows and solutions for leading edge designs and process nodes. Brian holds a BSEE from Seattle University.

Rama Lakamsani has over 30 years of experience working in CAD support, IC design flow and methodology areas after graduating with an MSEE from University of North Carolina, Charlotte. He joined ARM in 2011 as a Principal Applications Engineer specializing in implementation support. He currently manages a group supporting physical design of Arm processor cores and subsystems with responsibilities including training, consulting, development and customer service.

Desmond is AE Director responsible for technical engagements at ARM in the North America region enabling the deployment of Cadence’s Digital Implementation and Signoff solutions. In his 20 years with Cadence, Desmond supported a wide spectrum of customers with needs across the complete digital and signoff solutions space.

Rob Christy is a Technical Director and Distinguished Engineer at ARM working in the Central Engineering
Systems team to enable partners to build complex SoC. Rob believes in driving technical system solutions
by collaborating with ecosystem partners in the areas of IP, EDA and SW. After joining Arm in 2002 he has
worked on various SoC development platforms and CPUs eg. Cortex-A8, Cortex-A57. Bringing more than 28
years’ experience building these complex SoCs. Rob holds a Master of Science in VLSI Systems Engineering
from Manchester University (formerly UMIST), UK.

Sr. Product Engineering Group Director at Cadence Design Systems

Ajay Chopra is a Director for Design Enablement with the Physical Design Group at Arm, and is responsible for managing standard cells and I/O flows, and defining cloud strategy for the Physical Design Group. He has over 20 years of experience in the semiconductor industry, and started his career as a mask design engineer with STMicroelectronics, and later worked on automating various aspects of physical design, FPGA and embedded domains.

Praveen Patel, Director Product Engineering at Cadence, is part of the Digital Sign-off Group and leads product engineering and strategic customer engagements for Cadence’s Liberate tools. He has been with Cadence for more than 10 years. In his career which spans over more than two decades, he got multiple opportunities to work in various roles on both sides of the aisle – EDA vendor and User for EDA Solution – allowing him a unique perspective solving design challenges for Cadence customers.